MICROCHIP Core16550 Universal Asynchronous Receiver Transmitter

Okwu mmalite

Core16550 is a standard Universal Asynchronous Receiver-Transmitter (UART) that ensures software compatibility with the widely used 16550 device. It handles serial-to-parallel data conversion for inputs from modems or other serial devices and performs parallel-to-serial conversion for data sent from the CPU to these devices.
During transmission, data is written in parallel into the UART’s transmit First-In, First-Out (FIFO) buffer. The data is then serialized for output. When receiving, the UART converts incoming serial data into a parallel and enables easy access for the processor.
A typical application of the 16550 UART is illustrated in the following figure.

Figure 1. Typical 16550 Application

Isiokwu 1. Core16550 Nchịkọta

Atụmatụ igodo
Ndị a bụ njirimara isi nke Core16550:

• Transmitter and receiver are each buffered with upto 16-byte FIFOs to reduce the number of interrupts presented to the CPU.
• Adds or strips standard asynchronous communication bits (Start, Stop and Parity).
• Independently controlled transmit, receive, line status and data set interrupts
• Programmable baud generator
• Modem control functions (CTSn, RTSn, DSRn, DTRn, RIn and DCDn).
• Advanced Peripheral Bus (APB) ndebanye aha interface

Atụmatụ kwụsịrị
A ga-akwụsị nkwado nke Asụsụ Nkọwa Ngwaike (VHSIC) na ụdị nke a.
Core16550 Gbanwee ozi ndekọ
Akụkụ a na-enye nkọwa zuru okeview nke njirimara agbakwunyere ọhụrụ, malite na mwepụta kacha ọhụrụ.

Ụdị	Kedu nke pụtara ọhụrụ
Core16550 v3.4	Core16550 uses system verilog keyword “break” as register name which was causing syntax error issue. The keyword is replaced with another name to resolve this issue. Added PolarFire® family support
Core16550 v3.3	Added Radiation-tolerant FPGA (RTG4™) family support

1. Functional Block Description (Ask a Question)
   This section provides a short description for each element of the internal block diagram as displayed in the following figure.
   Figure 1-1. Core16550 Block Diagram
   

Ihe ndị dị na eserese ihe mgbochi ime (Jụọ ajụjụ)
Akụkụ na-esonụ na-enye ozi gbasara ihe ndị dị na eserese ngọngọ nke ime.

1. RWControl (Jụọ ajụjụ)
   Ihe mgbochi RWControl bụ maka ijikwa nkwukọrịta n'akụkụ akụkụ nke sistemu (parallel). A na-emecha ide na ịgụ akwụkwọ ndekọ aha niile site na ngọngọ a.
2. UART_Reg (Ask a Question)
   Ihe mgbochi UART_Reg na-ejide ndekọ ndekọ nke ngwaọrụ niile.
3. RXBlock (Jụọ ajụjụ)
   Nke a bụ ngọngọ nnabata. RXBlock na-enweta okwu nsonazụụ na-abata. Ọ bụ mmemme ịmata obosara data, dị ka 5, 6, 7 ma ọ bụ 8 ibe n'ibe; ntọala nha anya dị iche iche, dị ka ọbụna, ihe na-adịghị mma ma ọ bụ enweghị nha anya; na ibe nkwusi dị iche iche, dị ka 1, 1½ na 2 bits. RXBlock na-enyocha mperi na iyi data ntinye, dị ka mperi mperi, mperi mperi, mperi nbi na mperi. Ọ bụrụ na okwu na-abata enweghị nsogbu, a na-etinye ya na FIFO nnata.
4. Njikwa nkwụsị (Jụọ ajụjụ)
   Ihe mgbochi nkwụsịtụ na-eziga mgbama nkwụsị azụ na onye nrụpụta, dabere na steeti FIFO na data natara na bufee ya. Ndebanye aha nkwụsịtụ na-enye ọkwa nkwụsịtụ. A na-eziga nkwụsịtụ maka ihe nkwụnye ụgwọ / nnata efu (ma ọ bụ FIFO), njehie na ịnweta agwa, ma ọ bụ ọnọdụ ndị ọzọ chọrọ nlebara anya nke onye nrụpụta.
5. Baud Rate Generator (Jụọ ajụjụ)
   This block takes the input PCLK and divides it by a programmed value (from 1 to 216 – 1). The result is divided by 16 to create the transmission clock (BAUDOUT).
6. TXBlock (Jụọ ajụjụ)
   Ihe mgbochi Transmit na-ejikwa nnyefe data edere na Nyefee FIFO. Ọ na-agbakwụnye Mmalite, Parity na Kwụsị ibe n'ibe achọrọ na data a na-ebufe ka ngwaọrụ nnata nwee ike ime njikwa na ịnweta njehie kwesịrị ekwesị.

Ngwa ngwa ngwa (Jụọ ajụjụ)
Nkọwa ndekọ aha Core16550 na nkewa adreesị ka akọwara na ngalaba a. Tebụl na-esote na-egosi nchịkọta ndekọ aha Core16550.

PADDR [4:0] (Adreesi)	Nkeji Latch Access Bit1 (DLAB)	Aha	Akara	Default (reset) Value	No. of Bits	Gụọ/dee
00	0	Ndebanye aha nchekwa nnata	RBR	XX	8	R
00	0	Transmitter Holding Register	THR	XX	8	W
00	1	Latch nkewa (LSB)	DLR	01h	8	R/W
04	1	Latch nkewa (MSB)	DMR	00h	8	R/W
04	0	Kwụsị Kwado Ndebanye aha	IER	00h	8	R/W
08	X	Interrupt Identification Register	IIR	C1h	8	R
08	X	Ndebanye aha njikwa FIFO	FCR	01h	8	W
0C	X	Aha njikwa akara	LCR	00h	8	R/W
10	X	Ndebanye aha njikwa modem	MCR	00h	8	R/W
14	X	Ndebanye aha ahịrị	LSR	60h	8	R
18	X	Ndebanye aha modem	MSR	00h	8	R
1C	X	Ndebanye aha scratch	SR	00h	8	R/W

Ihe dị mkpa

DLAB is the MSB of the Line Control Register (LCR bit 7).

Receiver Buffer Register (Ask a Question)
A kọwapụtara ndekọ nchekwa nnata na tebụl na-esote.
Table 1-2. Receiver Buffer Register (Read Only)—Address 0 DLAB 0

Iberibe	Aha	Steeti izizi	Valid States	Ọrụ
7..0	RBR	XX	0...FFh	Iberibe data enwetara. Bit 0 bụ LSB, ma bụrụ nke mbụ natara.

Transmitter Holding Register (Ask a Question)
A kọwapụtara ndekọ njide ihe ntụgharị na tebụl na-esote.
Table 1-3. Transmitter Holding Register—Write Only

Iberibe	Aha	Steeti izizi	Valid States	Ọrụ
7..0	THR	XX	0...FFh	Ka ịnyefe ibe n'ibe data. Bit 0 bụ LSB, a na-ebufe ya na mbụ.

FIFO Control Register (Ask a Question)
A kọwapụtara ndekọ njikwa FIFO na tebụl na-esonụ.

Iberibe (7:0)	Steeti izizi	Valid States	Ọrụ
0	1	0, 1	Enables both the Transceiver (Tx) and Receiver (Rx) FIFOs. This bit must be set to 1 when other FCR bits are written to or they will not be programmed. 0: Agbanyụrụ 1: Agbanyere
1	0	0, 1	Clears all bytes in the Rx FIFO and resets its counter logic. The Shift register is not cleared. 0: Agbanyụrụ 1: Agbanyere
2	0	0, 1	Clears all bytes in the Tx FIFO and resets its counter logic. The Shift register is not cleared. 0: Agbanyụrụ 1: Agbanyere
3	0	0, 1	0: Otu mbufe DMA: Nyefe emere n'etiti okirikiri ụgbọ ala CPU 1: Multi-nyefe DMA: Nyefe mere ruo mgbe Rx FIFO efu ma ọ bụ Transmission System Operator (TSO) Nyefee (XMIT) FIFO jupụtara. Ekwesịrị ịtọ FCR[0] ka ọ bụrụ 1 ka ịtọọ FCR[3] ka ọ bụrụ 1.
4, 5	0	0, 1	Echekwara maka ojiji n'ọdịnihu.
6, 7	0	0, 1	These bits are used to set the trigger level for the Rx FIFO interrupt. 7 6 Rx FIFO Trigger Level (bytes) 0 0 01 0 1 04 1 0 08 1 1 14

Ndị na-edebanye aha njikwa nkewa (Jụọ ajụjụ)
A na-emepụta elekere Baud Rate (BR) site n'ikewa elekere ntinye aka (PCLK) site na 16 yana uru nkesa.

Tebụl na-esonụ depụtara example nke ụkpụrụ nkewa maka BR achọrọ mgbe ị na-eji elekere ntụaka 18.432 MHz.
Isiokwu 1-5. Nkeji Latch (LS na MS)

Iberibe	Aha	Steeti izizi	Valid States	Ọrụ
7..0	DLR	01h	01...FFh	The LSB of divisor value
7..0	DMR	00h	00...FFh	The MSB of divisor value

Isiokwu 1-6. Ọnụego Baud na ọnụ ahịa nkesa maka elekere ntụaka 18.432 MHz

Ọnụego Baud	Nkeji nkeji iri (Uru nkekọrịta)	Njehie pasentị
50	23040	0.0000%
75	15360	0.0000%
110	10473	-0.2865%
134.5	8565	0.0876%
150	7680	0.0000%
300	3840	0.0000%
600	1920	0.0000%
1,200	920	4.3478%
1,800	640	0.0000%

Ọnụego Baud	Nkeji nkeji iri (Uru nkekọrịta)	Njehie pasentị
2,000	576	0.0000%
2,400	480	0.0000%
3,600	320	0.0000%
4,800	240	0.0000%
7,200	160	0.0000%
9,600	120	0.0000%
19,200	60	0.0000%
38,400	30	0.0000%
56,000	21	-2.0408%

Interrupt Enable Register (Ask a Question)
Akọwapụtara aha ndekọ ike kwụsịrị na tebụl na-esote.
Isiokwu 1-7. Kwụsị Kwado Ndebanye aha

Iberibe	Aha	Steeti izizi	Valid State	Ọrụ
0	ERBFI	0	0, 1	Enables “Received Data Available Interrupt” 0: Disabled 1: Agbanyere
1	ETBEI	0	0, 1	Enables the “Transmitter Holding Register Empty Interrupt” 0: Disabled 1: Agbanyere
2	ELSI	0	0, 1	Enables the “Receiver Line Status Interrupt” 0: Disabled 1: Agbanyere
3	EDSSI	0	0, 1	Enables the “Modem Status Interrupt” 0: Disabled 1: Agbanyere
7..4	Echekwara	0	0	Mgbe niile 0

Interrupt Identification Register (Ask a Question)
The Interrupt Identification register is listed in the following table. Table 1-8. Interrupt Identification Register

Iberibe	Aha	Steeti izizi	Valid States	Ọrụ
3..0	IIR	1h	0..Ch	Interrupt identification bits.
5..4	Echekwara	00	00	Mgbe niile 00
7..6	Ụdị	11	11	11: FIFO mode

Akọwapụtara mpaghara ndekọ aha njirimara nkwụsịtụ na tebụl na-esonụ.

Isiokwu 1-9. Ogige ndebanye aha nbibi (IIR)

IIR Value[3:0)]	Ọkwa ebute ụzọ	Ụdị nkwụsị	Isi mmalite nkwụsị	Kwụsị njikwa nrụpụta
0110	Kachasị elu	Receiver line status	Overrun error, parity error, framing error or break interrupt	Ịgụ ndekọ ọnọdụ ahịrị
0100	Nke abụọ	Data enwetara dị	data nnata dị	Ịgụ ndekọ nchekwa nnata ma ọ bụ FIFO dara n'okpuru ọkwa mkpalite

Tebụl 1-9. Interrupt Identification Register Field (IIR) (continued)
IIR Value[3:0)]	Ọkwa ebute ụzọ	Ụdị nkwụsị	Isi mmalite nkwụsị	Kwụsị njikwa nrụpụta
1100	Nke abụọ	Ngosipụta oge ngwụcha nke agwa	Ọ nweghị mkpụrụedemede a na-agụ na Rx FIFO n'oge agwa anọ gara aga ma enwere opekata mpe otu agwa n'ime ya n'oge a.	Ịgụ ndekọ nchekwa nnata
0010	Nke atọ	Transmitter Holding register empty	Transmitter Holding register empty	Reading the IIR or writing into the Transmitter Holding register
0000	Nke anọ	Ọkwa modem	Kpochapụ ka izipu, data tọọ njikere, mgbanaka mgbanaka ma ọ bụ chọpụta onye na-ebu data	Reading the Modern Status register

 Line Control Register (Ask a Question)
The Line Control register is listed in the following table. Table 1-10. Line Control Register

Iberibe	Aha	Steeti izizi	Valid States	Ọrụ
1..0	WLS	0	0..3h	Ogologo Okwu Họrọ 00: 5 bit 01:6 ibe 10:7 ibe 11:8 ibe
2	STB	0	0, 1	Number of Stop Bits 0: 1 Stop bit 1: 1½ Stop bits when WLS = 00 2: Stop bits in other cases
3	IHE	0	0, 1	Parity Enable 0: Disabled 1: Agbanyere. A na-agbakwunye parity na nnyefe ma lelee na ịnata.
4	EPS	0	0, 1	Even Parity Select 0: Odd parity 1: Ọbụlagodi otu
5	SP	0	0, 1	Stick Parity 0: Disabled 1: Agbanyere Following are the parity details, when stick parity is enabled: Bits 4..3 11: 0 ka a ga-eziga dị ka ihe nrịbama nke Parity, wee lelee na ịnata. 01: 1 ka a ga-eziga dị ka ihe nrịbama nke Parity, wee lelee na ịnata.
6	SB	0	0, 1	Set Break 0: Disabled 1: Tọọ ezumike. A na-amanye SOUT ka ọ bụrụ 0. Nke a enweghị mmetụta ọ bụla na mgbagha transmitter. Agbanyụrụ ezumike ahụ site na ịtọọ ntakịrị ka ọ bụrụ 0.
7	DLAB	0	0, 1	Nkeji Latch Access Bit 0: Agbanyụrụ. Ụdị okwu nkịtị na-eji. 1: Agbanyere. Na-enye ohere ịnweta ndekọ ndekọ nke Divisor Latch n'oge a na-agụ ma ọ bụ dee iji adreesị 0 na 1.

Modem Control Register (Ask a Question)
Edepụtara aha njikwa modem na tebụl na-esonụ.

Iberibe	Aha	Steeti izizi	Valid States	Ọrụ
0	DTR	0	0, 1	Controls the Data Terminal Ready (DTRn) output. 0: DTRn <= 1 1: DTRn <= 0
1	RTS	0	0, 1	Controls the Request to Send (RTSn) output. 0: RTSn <= 1 1: RTSn <= 0
2	Mpụ1	0	0, 1	Controls the Output1 (OUT1n) signal. 0: OUT1n <= 1 1: OUT1n <= 0
3	Mpụ2	0	0, 1	Controls the Output2 (OUT2n) signal. 0: OUT2n <= 1 1: OUT2n <= 0
4	Loop	0	0, 1	Loop enable bit 0: Disabled 1: Agbanyere. Ihe ndị a na-eme na ọnọdụ Loop: SOUT is set to 1. The SIN, DSRn, CTSn, RIn and DCDn inputs are disconnected. The output of the Transmitter Shift register is looped back into the Receiver Shift register. The modem control outputs (DTRn, RTSn, OUT1n and OUT2n) are connected internally to the modem control inputs, and the modem control output pins are set at 1. In Loopback mode, the transmitted data is immediately received, allowing the CPU to check the operation of the UART. The interrupts are operating in Loop mode.
7..4	Echekwara	0h	0	Echekwara

Line Status Register (Ask a Question)
A kọwapụtara ndekọ aha ahịrị na tebụl na-esonụ.
Table 1-12. Line Status Register—Read Only

Iberibe	Aha	Steeti izizi	Valid States	Ọrụ
0	DR	0	0, 1	Ihe ngosi njikere data 1 when a data byte has been received and stored in the receive buffer or the FIFO. DR is cleared to 0 when the CPU reads the data from the receive buffer or the FIFO.
1	OE	0	0, 1	Ngosipụta mperi Indicates that the new byte was received before the CPU read the byte from the receive buffer, and that the earlier data byte is destroyed. OE is cleared when the CPU reads the Line Status register. If the data continues to fill the FIFO beyond the trigger level, an overrun error occurs once the FIFO is full and the next character has been completely received in the Shift register. The character in the Shift register is overwritten, but it is not transferred to the FIFO.
2	PE	0	0, 1	Ngosipụta mperi mkọrịta Indicates that the received byte had a parity error. PE is cleared when the CPU reads the Line Status register. This error is revealed to the CPU when its associated character is at the top of the FIFO.
3	FE	0	0, 1	Ngosi mperi mperi Indicates that the received byte did not have a valid Stop bit. FE is cleared when the CPU reads the Line Status register. The UART will try to resynchronize after a framing error. To do this, it assumes that the framing error was due to the next Start bit, so it samples this Start bit twice, and then starts receiving the data. This error is revealed to the CPU when its associated character is at the top of the FIFO.

Isiokwu 1-12. Line Status Register—Read Only (continued)
Iberibe	Aha	Steeti izizi	Valid States	Ọrụ
4	BI	0	0, 1	Ihe ngosi nkwụsịtụ Na-egosi na data enwetara dị na 0, ogologo karịa oge nnyefe okwu zuru oke (Malite bit + Data bits + Parity + Stop bits). BI is cleared when the CPU reads the Line Status register. This error is revealed to the CPU when its associated character is at the top of the FIFO. When break occurs, only one zero character is loaded into the FIFO.
5	ATO	1	0, 1	Ngosipụta Njide Jide Ndebanye aha efu (THRE). Indicates that the UART is ready to transmit a new data byte. THRE causes an interrupt to the CPU when bit 1 (ETBEI) in the Interrupt Enable register is 1. This bit is set when the TX FIFO is empty. It is cleared when at least one byte is written to the TX FIFO.
6	TEMT	1	0, 1	Ngosipụta ihe efu Edobere ntakịrị a ka ọ bụrụ 1 mgbe ma ndị na-ebufe FIFO na ndekọ Shift tọgbọrọ chakoo.
7	FIER	0	1	This bit is set when there is at least one parity error, framing error or break indication in the FIFO. FIER is cleared when the CPU reads the LSR if there are no subsequent errors in the FIFO.

Modem Status Register (Ask a Question)
Edepụtara aha ọnọdụ modem na tebụl na-esonụ.
Table 1-13. Modem Status Register—Read Only

Iberibe	Aha	Steeti izizi	Valid States	Ọrụ
0	DCTS	0	0, 1	Delta Clear ka izipu egosi. Indicates that the CTSn input has changed state since the last time it was read by the CPU.
1	DDSR	0	0, 1	Ihe ngosi Nhazi Njikere Data Delta Indicates that the DSRn input has changed state since the last time it was read by the CPU.
2	TRI	0	0, 1	Trailing Edge of Ring Indicator detector. Indicates that RI input has changed from 0 to 1.
3	DDCD	0	0, 1	Delta Data Carrier Detect indicator Indicates that DCD input has changed state. Mara: Mgbe ọ bụla 0, 1, 2 ma ọ bụ 3 atọrọ na 1, a na-ewepụta nkwụsịtụ ọnọdụ modem.
4	CTS	0	0, 1	Kpochapụ izipu The complement of the CTSn input. When bit 4 of the Modem Control Register (MCR) is set to 1 (loop), this bit is equivalent to DTR in the MCR.
5	DSR	0	0, 1	Data Njikere The complement of the DSR input. When bit 4 of the MCR is set to 1 (loop), this bit is equivalent to RTSn in the MCR.
6	RI	0	0, 1	Ihe ngosi mgbanaka The complement of the RIn input. When bit 4 of the MCR is set to 1 (loop), this bit is equivalent to OUT1 in the MCR.
7	DCD	0	0, 1	Chọpụta onye na-ebu data The complement of DCDn input. When bit 4 of the MCR is set to 1 (loop), this bit is equivalent to OUT2 in the MCR.

Scratch Register (Ask a Question)
A kọwapụtara ndekọ Scratch na tebụl na-esonụ.

Iberibe	Aha	Steeti izizi	Ọrụ
7..0	SCR	00h	Read/Write register for CPU. No effects on UART operation.

Ngwa ngwa na-aga (Jụọ ajụjụ)
Nkebi a na-enye nkọwa gbasara ngwa ngwa ngwa.

 SmartDesign (Jụọ ajụjụ)
Core16550 dị maka nbudata na SmartDesign IP nhazi gburugburu imewe. A na-ahazi isi ya site na iji GUI nhazi n'ime SmartDesign, lee foto ndị a.
Maka ozi gbasara otu esi eji SmartDesign mee ngwa ngwa, hazie, jikọọ na imepụta cores, hụ ntuziaka onye ọrụ SmartDesign.

Ọgụgụ 2-1. Nhazi Core16550 

Na-aga ịme anwansị (Jụọ ajụjụ)
Agụnyere testbench onye ọrụ maka Core16550 na mwepụta niile.
Iji na-agba simulations, họrọ User Testbench Flow nhọrọ n'ime SmartDesign wee pịa N'ịwa imewe n'okpuru SmartDesign menu. A na-ahọpụta testbench onye ọrụ site na Core Testbench Configuration GUI.
Mgbe SmartDesign weputara oru Libero SoC, ọ na-etinye testbench onye ọrụ files.
Iji mee testbench onye ọrụ, tọọ mgbọrọgwụ imewe na ngwa ngwa Core16550 na Libero SoC Design Hierarchy pane wee pịa akara ngosi Simulation na windo SoC Design Flow. Nke a na-akpọ ModelSim® ma na-eme ihe ngosi ahụ na-akpaghị aka.

Synthesis in Libero SoC (Ask a Question)
Click the Synthesis icon in Libero SoC. The Synthesis window appears. The Synplify® project. Set Synplify to use the Verilog 2001 standard if Verilog is being used. To run Synthesis, click the Run icon.

Ebe-na ụzọ na Libero SoC (Jụọ ajụjụ)
Ka ịtọọ ụzọ nhazi ahụ nke ọma wee mee Synthesis, pịa akara ngosi okirikiri nhọrọ ukwuu na Libero SoC wee kpọọ onye nrụpụta. Core16550 anaghị achọ ntọala ebe na ụzọ pụrụ iche.

Core16550 (Jụọ ajụjụ)

Akụkụ a na-enye ozi gbasara paramita ejiri na isi a.

Parameters (Jụọ ajụjụ)
Core16550 anaghị akwado paramita ọ bụla dị elu.

Isi interface (Jụọ ajụjụ)

Akụkụ a na-enye nchịkọta ntinye na mmepụta.

Nkọwa mgbaàmà I/O (Jụọ ajụjụ)
Ndị a na-edepụta nkọwapụta Core16550 I/O.

Aha	Ụdị	Polarity	Nkọwa
PRESETN	Ntinye	Dị ala	Ntọgharị nna ukwu
PCLK	Ntinye	—	Master elekere PCLK is divided by the value of the Divisor registers. The result is then divided by 16 to produce the baud rate. The resultant signal is the BAUDOUT signal. The rising edge of this pin is used to strobe all input and output signals.
Idee	Ntinye	Elu	APB write/read enable, active-high. When HIGH, data is written to the specified address location. When LOW, data is read from the specified address location.
PADDR [4:0]	Ntinye	—	APB Address This bus provides the link for the CPU to the address of the register of Core16550 to be read from or written to.
PSEL	Ntinye	Elu	APB select When this is HIGH along with PENABLE, reading and writing to Core16550 is enabled.
PWDATA[7:0]	Ntinye	—	Data input bus Data on this bus will be written into the addressed register during a write cycle.
AKWỤKWỌ	Ntinye	Elu	APB enable When this is HIGH along with PSEL, reading and writing to Core16550 is enabled.
PRDATA[7:0]	Mpụta	—	Data output bus This bus holds the value of the addressed register during a read cycle.
CTSn	Ntinye	Dị ala	Kpochapụ izipu This active-low signal is an input showing when the attached device (modem) is ready to accept data. Core16550 passes this information to the CPU through the Modem Status register. This register also indicates that if the CTSn signal has changed since the last time, the register was read.
DSRn	Ntinye	Dị ala	Data Njikere This active-low signal is an input indicating when the attached device (modem) is ready to set up a link with Core16550. Core16550 passes this information to the CPU through the Modem Status register. This register also indicates if the DSRn signal has changed since the last time the register was read.
DCDn	Ntinye	Dị ala	Chọpụta onye na-ebu data This active-low signal is an input indicating when the attached device (modem) has detected a carrier. Core16550 passes this information to the CPU though the Modem Status register. This register also indicates if the DCDn signal has changed since the last time the register is read.
Mmehie	Ntinye	—	Data Ntinye Oghere Usoro A na-ebufe data a na Core16550. Ejikọrọ ya na ntụtụ ntinye PCLK.
RIN	Ntinye	Dị ala	Ihe ngosi mgbanaka This active-low signal is an input showing when the attached device (modem) has sensed a ring signal on the telephone line. Core16550 passes this information to the CPU through the Modem Status register. This register also indicates when the RIn trailing edge was sensed.
ỊGỤ	Mpụta	—	Serial output data This data is transmitted from Core16550. It is synchronized with the BAUDOUT output pin.
RTSn	Mpụta	Dị ala	Arịrịọ izipu This active-low output signal is used to inform the attached device (modem) that Core16550 is ready to send data. It is programmed by the CPU through the Modem Control register.

Isiokwu 4-1. I/O Signal Summary (continued)
Aha	Ụdị	Polarity	Nkọwa
DTRn	Mpụta	Dị ala	Njikere ọdụ data This active-low output signal informs the attached device (modem) that Core16550 is ready to establish a communications link. It is programmed by the CPU through the Modem Control register.
Mpụ1n	Mpụta	Dị ala	Mmepụta 1 This active-low output is a user-defined signal. CPU programs this signal through the Modem Control register and is set to the opposite value.
Mpụ2n	Mpụta	Dị ala	Mmepụta 2 This active-low output signal is a user-defined signal. It is programmed by the CPU through the Modem Control register and is set to the opposite value. programmed.
INTR	Mpụta	Elu	Interrupt Pending This active-high output signal is the interrupt output signal from Core16550. It is programmed to become active on certain events, informing the CPU that such an event has occurred, (for more details, see Interrupt Identification Register). The CPU then takes appropriate action.
BAUDOUTn	Mpụta	Dị ala	Baud out This is an output clock signal derived from the input clock for synchronizing the data output stream from SOUT.
RXRDYN	Mpụta	Dị ala	Receiver ready to receive transmissions. The CPU is indicated by this active-low output signal that the receiver section of Core16550 is available for data to be read.
TXRDYN	Mpụta	Dị ala	Transmitter ready to transmit data. This active-low signal indicates to the CPU that the transmitter section of Core16550 has space to write data for transmission.
rxfifo_empty	Mpụta	Elu	Receive FIFO empty. This signal goes HIGH when the receive FIFO is empty.
rxfifo_full	Mpụta	Elu	Receive FIFO full. This signal goes High when the receive FIFO is full.

Eserese oge (Jụọ ajụjụ)
Akụkụ a na-enye eserese oge nke isi a.

 okirikiri dee data na okirikiri ọgụgụ data (Jụọ ajụjụ)
Ọgụgụ 5-1 na eserese 5-2 na-egosipụta okirikiri ederede na gụpụta mmekọrịta oge okirikiri metụtara elekere sistemụ APB, PCLK.

Debanye aha dee (jụọ ajụjụ)
Ọnụọgụ na-esonụ na-egosi Adreesị, Họrọ na Kwado akara na-adachiri ma ga-adị irè tupu oke PCLK na-ebili. Edemede na-apụta na nsọtụ mgbama PCLK na-arị elu.

Debanye aha Gụọ (jụọ ajụjụ)
Ọnụọgụ na-esonụ na-egosi Adreesị, Họrọ na Kwado akara na-adachiri ma ga-adị irè tupu oke PCLK na-ebili. Ọgụgụ na-apụta na nsọtụ mgbama PCLK na-arị elu. Maka nkọwa ndị ọzọ na nkọwapụta na oge ebili mmiri, hụ nkọwapụta AMBA.

Mmekọrịta nnata (Jụọ ajụjụ)
Mgbe onye nnata chọpụtara ọnọdụ dị ala na iyi data na-abata, ọ ga-emekọrịta na ya. Mgbe mmalite mmalite, UART na-echere 1.5 × (ogologo oge nkịtị). Nke a na-eme ka a gụọ ntakịrị nke ọ bụla na-esote n'etiti obosara ya. Ọnụ ọgụgụ na-esonụ na-egosi usoro mmekọrịta a.

Ọgụgụ 5-3. Mmekọrịta nnata

Ọrụ Testbench (Jụọ ajụjụ)
Naanị otu testbench ka enyere ya na Core16550: Verilog user testbench. Nke a bụ testbench dị mfe iji dee na Verilog. Emebere testbench a maka mgbanwe ndị ahịa.

Testbench onye ọrụ (Jụọ ajụjụ)
Ọnụ ọgụgụ na-esonụ na-egosi eserese ngọngọ nke example onye ọrụ imewe na testbench.
Ọgụgụ 6-1. Testbench onye ọrụ Core16550

Testbench onye ọrụ gụnyere example imewe nke na-eje ozi dị ka ntụaka maka ndị ọrụ na-achọ ka mejuputa ha onwe ha aghụghọ.
The testbench maka example, user design implements a subset of the functionality tested in the verification testbench, for more details, see User Testbench. Conceptually, as shown in Figure 6-1, the instantiation of Core16550 is simulated using a behavioral microcontroller and a simulated loopback connection. For example, testbench onye ọrụ na-egosiputa nnyefe na ịnweta site na otu Core16550 unit, yabụ ị nwere ike nweta nghọta bụ isi nke otu esi eji isi a.
Testbench onye ọrụ na-egosipụta ntọala ntọala, bufee na nata arụmọrụ nke Core16550. Testbench onye ọrụ na-eme usoro ndị a:

1. Write to the control registers.
2. Check received data.
3. Turn on transmit and receive.
4. Read the control registers.
5. Transmit and receive one byte.

Iji ngwaọrụ na arụ ọrụ (Jụọ ajụjụ)

The following table lists the Core16550 utilization and performance data. Table 7-1. Core16550 Utilization and Performance PolarFire and PolarFire SoC

Nkọwa ngwaọrụ		Akụrụngwa			RAM
Ezinụlọ	Ngwaọrụ	4LUT	DFF	Ihe mgbagha	μSRAM
PolarFire®	MPF100T-FCSG325I	752	284	753	2
PolarFire®SoC	MPFS250TS- FCSG536I	716	284	720	2
RTG4™	RT4G150-1CG1657M	871	351	874	2
IGLOO® 2	M2GL050TFB GA896STD	754	271	1021	2
SmartFusion® 2	M2S050TFBG A896STD	754	271	1021	2
SmartFusion®	A2F500M3G- STD	1163	243	1406	2
IGLOO®/IGLOOE	AGL600- STD/AGLE600 V2	1010	237	1247	2
Ngwakọta	AFS600-STD	1010	237	1247	2
ProASIC® 3/E	A3P600-STD	1010	237	1247	2
ProASIC Plus®	APA075-STD	1209	233	1442	2
RTAX-S	RTAX250S- STD	608	229	837	2
Axcelerator®	AX125-STD	608	229	837	2

Okwu edoziziri (Jụọ ajụjụ)
Tebụlụ na-esote depụtara okwu niile edoziziri maka mwepụta Core16550 dị iche iche.
Isiokwu 8-1. Okwu edoziziri

Ụdị	Mgbanwe
v3.4	Core16550 uses System Verilog Keyword “break” as register name which was causing syntax error issue. This has been fixed by replacing the keyword with another name. Added PolarFire® family support

Akụkọ ngbanwe (Jụọ ajụjụ)

Akụkọ ngbanwe ahụ na-akọwa mgbanwe ndị etinyere na akwụkwọ ahụ. Edepụtara mgbanwe ndị a site na ntughari, malite na mbipụta kachasị ugbu a.

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Kpọtụrụ Ụlọ Ọrụ Nkwado nka na ụzụ site na websaịtị na www.microchip.com/support Kwuo nọmba akụkụ ngwaọrụ FPGA, họrọ udi ikpe dabara adaba, wee bulite imewe files mgbe ị na-ekepụta ikpe nkwado teknụzụ.
Kpọtụrụ ọrụ ndị ahịa maka nkwado ngwaahịa na-abụghị teknụzụ, dị ka ọnụahịa ngwaahịa, nkwalite ngwaahịa, mmelite ozi, ọkwa ịtụ na ikike.

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Akwụkwọ / akụrụngwa

MICROCHIP Core16550 Universal Asynchronous Receiver Transmitter [pdf] Ntuziaka onye ọrụ v3.4, v3.3, Core16550 Universal Asynchronous Receiver Transmitter, Core16550, Universal Asynchronous Receiver Transmitter, Asynchronous Receiver Transmitter, Asynchronous Receiver Transmitter, Receitter Transmitter, Transmitter

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