GOWIN IPUG1205 SDI Encoder IP
Nwebiisinka 2025 Guangdong Gowin Semiconductor Corporation. Ikike niile echekwabara.
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Nkwuputa
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Akụkọ ngbanwe
| Ụbọchị | Ụdị | Nkọwa |
| 04/11/2025 | 1.0E | Ebipụtara ụdị izizi. |
Banyere Nduzi a
Ebumnuche
Ebumnuche nke Gowin SDI Encoder IP bụ iji nyere gị aka ịmụta njirimara na ojiji nke Gowin SDI Encoder IP site n'inye nkọwa nke njirimara, ọrụ, ọdụ ụgbọ mmiri, oge, GUI na ntinye akwụkwọ, wdg. Ihe nseta ihuenyo software na ngwaahịa ndị akwadoro edepụtara na akwụkwọ ntuziaka a dabeere na Gowin Software 1.9.11 (64-bit). Ebe ọ bụ na ngwanro ahụ nwere ike ịgbanwe n'enweghị ọkwa, ụfọdụ ozi nwere ike ọ gaghị adị mkpa yana enwere ike idozi ya dịka ngwanro eji arụ ọrụ.
Akwụkwọ ndị emetụtara
Ntuziaka onye ọrụ kacha ọhụrụ dị na GOWINSEMI websaịtị. Ị nwere ike ịchọta akwụkwọ ndị metụtara ya na www.gowinsemi.com:
- DS981, GW5AT usoro nke akwụkwọ data ngwaahịa ngwaahịa FPGA
- DS1239, GW5AST usoro nke akwụkwọ data ngwaahịa ngwaahịa FPGA
- SUG100, ntuziaka onye ọrụ ngwanrọ Gowin
Okwu okwu na ndebiri
Tebụl 1-1 na-egosi ndebiri na okwu okwu ejiri n'akwụkwọ ntuziaka a.
Tebụl 1-1 Okwu okwu na ndebiri
| Okwu okwu na ndebiri | Pụtara |
| DE | Kwado data |
| FPGA | Nhazi Ọnụ Ụzọ Ámá Mmemme |
| HS | Mmekọrịta kwụ ọtọ |
| IP | Arịa ọgụgụ isi |
| SDI | Oghere Usoro dijitalụ Interface |
| SerDes | Serializer/Deserializer |
| SMPTE | Society of Motion Picture and Television Engineers |
| VESA | Video Electronics Standard Association |
| VS | Mmekọrịta kwụ ọtọ |
Nkwado na nzaghachi
Gowin Semiconductor na-enye ndị ahịa nkwado teknụzụ zuru oke. Ọ bụrụ na ị nwere ajụjụ, nkọwa ma ọ bụ aro ọ bụla, biko nweere onwe gị ịkpọtụrụ anyị ozugbo site na iji ozi enyere n'okpuru.
Websaịtị: www.gowinsemi.com Email: support@gowinsemi.com
gafereview
Serial Digital Interface (SDI) bụ otu n'ime ezinaụlọ interface vidiyo dijitalụ ma ejiri ya maka ịnyefe akara vidiyo dijitalụ. Enwere ike ịrụ ọrụ Gowin SDI Encoder IP n'okpuru HD ma ọ bụ ụkpụrụ ọnụego 3G nke Society of Motion Picture and Television Engineers kọwara (SMPTE), na-atụgharị akara ngosi vidiyo na akara SDI.
Tebụl 2-1 Gowin SDI Encoder IP
| Gowin SDI Encoder IP | |
| Ihe enyemaka | Biko rụtụ aka na tebụl 2-2. |
| Ebutere Doc. | |
| Nhazi Files | Verilog (ezoro ezo) |
| Atụmatụ ntụaka | Verilog |
| TestBench | Verilog |
| Nnwale na nhazi usoro | |
| Ngwa nke synthesis | GowinSynthesis |
| Ngwa ngwa | Gowin Software (V1.9.11 na n'elu) |
Mara!
Maka ngwaọrụ ndị akwadoro, ị nwere ike pịa Ebe a iji nweta ozi.
Atụmatụ
- Na-arụ ọrụ na 1 ụzọ
- Na-akwado ọnụego njikọ nke 1.485/2.97 Gbps kwa uzo
- Na-akwado HD-SDI na 3G-SDI
Iji akụrụngwa
Gowin SDI Encoder IP can be implemented by Verilog. Its performance and resource utilization may vary when the design is employed in different devices, or at different densities, speeds, or grades. Taking Gowin GW5AST series of FPGA as an instance, the resource utilization of Gowin SDI Encoder IP is as shown in Table 2-2.
Tebụl 2-2 Gowin SDI Encoder IP akụrụngwa itinye n'ọrụ
| Ngwaọrụ | GW5AST-60 |
| Debanye aha | 629 |
| LUT | 1015 |
Nkọwa ọrụ
Eserese ngọngọ Sistemu
Gowin SDI Encoder IP nwere ike ịtụgharị akara ngosi vidiyo ka ọ bụrụ akara SDI. A na-ejikọta akara SDI na SDI PHY IP. Eserese ngọngọ nke Gowin SDI Encoder IP dị ka egosiri na eserese 3-1.
Figure 3-1 Gowin SDI Encoder IP Block Diagram
Modul ọrụ
Figure 3-2 Gowin SDI Encoder IP Block Diagram
Dị ka egosiri na eserese dị n'elu, Gowin SDI Encoder IP nwere ike ịtụgharị data vidiyo na data SDI.
Ụdị akwadoro
Tebụl 3-1 na-egosi ụdị nke Gowin SDI Encoder IP kwadoro.
Tebụl 3-1 Ụdị nke Gowin SDI Encoder IP kwadoro
| Ọkọlọtọ | HD-SDI | 3G-SDI | |||||
| Pixel Hor Addr | 1280 | 1280 | 1920 | 1920 | 1920 | 1920 | 1920 |
| Ver Addr Line | 720 | 720 | 1080 | 1080 | 1080 | 1080 | 1080 |
| Ngụkọta Pixel | 1650 | 1980 | 2200 | 2640 | 2750 | 2200 | 2640 |
| Ọkọlọtọ | HD-SDI | 3G-SDI | |||||
| Ver ngụkọta ahịrị | 750 | 750 | 1125 | 1125 | 1125 | 1125 | 1125 |
| Ọnọdụ nyocha | Progressi ve | Progressi ve | Progressi ve | Progressi ve | Progressi ve | Progressi ve | Progressi ve |
| Ọnụego Frame | 60 | 50 | 30 | 25 | 24 | 60 | 50 |
| Bit kwa Okwu | 20 | 20 | 20 | 20 | 20 | 20 | 20 |
| Ọnụego okwu (Mhz) | 74.25 | 74.25 | 74.25 | 74.25 | 74.25 | 148.5 | 148.5 |
| Pixel SampỌnụ ego (Mhz) | 74.25 | 74.25 | 74.25 | 74.25 | 74.25 | 148.5 | 148.5 |
| Nhazi | YC4:2:2 | YC4:2:2 | YC4:2:2 | YC4:2:2 | YC4:2:2 | YC4:2:2 | YC4:2:2 |
| Omimi Pixel | 10 | 10 | 10 | 10 | 10 | 10 | 10 |
Ndepụta Port
E gosipụtara ọdụ ụgbọ mmiri IO nke Gowin SDI Encoder IP na eserese 3-3.
Figure 3-3 Gowin SDI Encoder IP Port Diagram
Ọdụ ụgbọ mmiri IO na-adịgasị iche dabere na paramita.
E gosipụtara nkọwa nke ọdụ ụgbọ mmiri IO nke Gowin SDI Encoder IP na tebụl 3-2.
Isiokwu 3-2 I/O Ndepụta nke Gowin SDI Encoder IP
| Aha mgbaàmà | I/O | Ogologo data | Nkọwa |
| Mbụ_n | I | 1 | Tọgharia mgbaama, arụ ọrụ-ala |
| I_rate | I | 3 | Rate input: 0: Reserved
1: HD-SDI 2: 3G-SDI |
| I_hres | I | 16 | Ntinye mkpebi kwụ ọtọ |
| I_vres | I | 16 | Ntinye mkpebi kwụ ọtọ |
| I_ver_fre | I | 3 | Vertical frequency input: 0: 60Hz
1: 50Hz 2: 30Hz 3: 25Hz 4: 24Hz |
| I_interlace | I | 1 | Interlace input:
0: echekwabara 1: Progressive scan P |
| I_color | I | 1 | Color input: 0: YC
1: echekwabara |
|
I_mfactor |
I | 1 | N factor input: 0: M = 1
1: echekwabara |
| I_pixbit | I | 1 | Pixel bit input: 0: 10bit
1: echekwabara |
| I_pixstruc | I | 2 | Pixel structure input: 2’b00: 4:2:2
2'b01: Echekwara 2'b10: Echekwara 2'b11: echekwabara |
| I_clk | I | 1 | Input clock |
| I_fld | I | 1 | Field input (odd/even) |
| I_vs | I | 1 | vs input (positive polarity) |
| I_hs | I | 1 | hs input (positive polarity) |
| I_de | I | 1 | de input |
| I_data | I | 20 | Ntinye data |
| O_data | O | 80 | The encoded data, connected to the SDI PHY IP. |
Nkọwa oge
The input interface timing diagram of Gowin SDI Encoder IP is as shown in Figure 3-4. For standard video, simply input the signals, and Gowin SDI Encoder IP will encode them. The encoded data is then output to the SDI PHY IP.
Ọgụgụ 3-4 eserese oge nke Interface ntinye vidiyo
Nhazi interface
Ị nwere ike iji IP core generator ngwá ọrụ na Gowin Software ịkpọ na hazie Gowin SDI Encoder IP.
Mepee IP Core Generator
Mgbe ịmepụtara ọrụ ahụ, pịa taabụ "Ngwaọrụ" dị n'aka ekpe elu, pịa "IP Core Generator" site na listi ndọpụta iji mepee Gowin IP Core Generator, dị ka egosiri na Figure 4-1.
Ọgụgụ 4-1 Mepee IP Core Generator
Họrọ SDI Encoder IP.
Pịa ugboro abụọ "Multimedia" wee họrọ SDI Encoder ka imepe SDI Encoder IP nhazi interface, dị ka egosiri na eserese 4-2.
Figure 4-2 Select SDI Encoder IP
Gowin SDI Encoder IP Configuration Interface
First configure “General” tab in the SDI Encoder IP interface as shown in Figure 4-3.
- Ngwaọrụ, Ụdị ngwaọrụ, Nọmba akụkụ: Ntọala nọmba akụkụ, nke ọrụ dị ugbu a kpebiri, onye ọrụ enweghị ike ịtọ ya.
- Language: Supports Verilog and VHDL; choose the language as requirements, and the default is Verilog.
- File Name, Module Name, Create In: Displays SDI file aha, modul aha na emepụtara file uzo.
Figure 4-3 Gowin SDI Encoder IP Configuration Interface
Pịa "OK" ozugbo ka ịmepụta IP.
Atụmatụ ntụaka
This chapter is intended to introduce the usage and structure of the reference design of Gowin SDI Encoder IP. Please see the SDI PHY IP Reference Design for details at Gowinsemi websaịtị.
Atụmatụ ntụaka a na-ewe DK_START_GW5AT-LV60PG484A_V1.1 dị ka bọọdụ mmepe.ample. For more information about
DK_START_GW5AT-LV60PG484A_V1.1 development board, please refer to Gowinsemi websaịtị. E gosipụtara eserese ngọngọ nke nhazi ntụaka na eserese 5-1.
Onyonyo 5-1 Block Eserese nke Nrụtụ aka
File Nnyefe
Nke file nnyefe maka Gowin SDI Encoder IP na-agụnye akwụkwọ, koodu isi mmalite, na nhazi ntụaka.
Akwụkwọ
Tebụl 6-1 Ndepụta akwụkwọ
| Aha | Nkọwa |
| IPUG1025, Gowin SDI Encoder IP ntuziaka onye ọrụ | Gowin SDI Encoder IP ntuziaka onye ọrụ, ya bụ, akwụkwọ ntuziaka a. |
Koodu Isi mmalite chepụta (Ezo ya ezo)
Mpempe koodu ezoro ezo nwere koodu RTL ezoro ezo maka Gowin SDI Encoder IP. Ezubere koodu a maka iji GUI wepụta isi IP dịka achọrọ.
Tebụl 6-2 File Ndepụta nke Gowin SDI Encoder IP
| Aha | Nkọwa |
| sdi_encoder.v | SDI Decoder IP File, ezoro ezo. |
Atụmatụ ntụaka
The RefDesign folder contains the netlist files, atụmatụ ntụaka onye ọrụ, mgbochi files, elu-ọkwa files, na oru ngo files maka Gowin SDI PHY IP, Gowin SDI Encoder IP, na Gowin SDI Decoder IP.
Table 6-2 Gowin SDI Encoder IP RefDesign Folder Content List
| Aha | Nkọwa |
| vidiyo_top.v | Modul kacha elu nke nrụtụ aka imewe |
| testpattern.v | Nnwale mmepụta modul |
| dk_video.cst | Ihe mgbochi anụ ahụ Project file |
| dk_video.sdc | Ihe mgbochi oge oru ngo file |
| igodo_debounceN.v | Mwepu igodo |
| adv7513_iic_init.v | adv7513 nhazi file |
| yc_to_rgb | yc_to_rgb nchekwa |
| rgb_to_yc | rgb_to_yc nchekwa |
| i2c_onye isi | I2c_master nchekwa, ezoro ezo. |
IPUG1205-1.0E, 04/11/2025
Akwụkwọ / akụrụngwa
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GOWIN IPUG1205 SDI Encoder IP [pdf] Ntuziaka onye ọrụ IPUG1205-1.0E, IPUG1205 SDI Encoder IP, SDI Encoder IP, Encoder IP |